The non-volatile memory function of EPROM memories is based on the storage of charge. EPROM memory transistors are all of the floating gate type, which means that the charge is stored on an additional polysilicon layer, located between the control gate and the substrate of a transistor. This type of memory cell can consist of only one transistor. The presence or absence of charge on the floating gate determines whether the cell will conduct current or not, which defines the two logic states. Present EPROM devices all use channel hot electron (CHE) injection to bring electrons onto the floating gate, and ultra-violet (UV) light is used to erase the memory. CHE injection programming is accomplished by applying a higher voltage (12 V) to the cell control gate. CHE programming is also used to store charge on flash-EPROMs. Another non-volatile memory floating gate device is the electrically erasable read-only memory (EEPROM) which is also programmed with the 12 volt gate signal.
In the IC chip industry, it is a continuing objective to reduce the size of each individual cell to allow packing more devices on a single chip, i.e., higher density. Since it has become clear that CHE programmable transistors are to be used in high-density EPROMs, technology has been adapted in order to yield fast-programmable, high-density floating gate EPROM structures. The efficiency of the CHE programming process is largely dependent on substrate (and drain junction) doping level, effective channel length, and floating gate-drain junction overlap. One method that can achieve high density is by using the self-aligned double polysilicon stacked gate structure, in which the drain/source junctions are self-aligned with respect to the floating gate and in which the double polysilicon stacked gate structure is etched in one step, usually by means of an anisotropic dry etching process.
There are certain problems associated with extremely short channels. Included in these so-called "short channel effects" are: (1) failure of the drain current to saturate at large V.sub.DS ; (2) increased subthreshold current; (3) reduction of threshold voltage V.sub.t ; and (4) in the extreme, a loss of the ability of the gate to control gain. Consequently, much of the present-date MOSFET design effort is devoted to producing transistors that are physically small but still exhibit the electrical characteristics similar to those of physically long channels.
It is the purpose of this invention to provide a memory cell of minimal surface area, i.e., one square micron or less, yet maintain the electrical characteristics of a larger area device.